------------------------------------------------------------------------
r3950 | balrog | 2008-02-02 20:42:36 -0600 (Sat, 02 Feb 2008) | 2 lines
Changed paths:
   M /trunk/target-i386/cpu.h
   M /trunk/target-i386/helper.c

Make SVM env->cr[8] a valid register (patch from TeLeMan).

 ------------------------------------------------------------------------
Index: target-i386/helper.c
===================================================================
--- target-i386/helper.c	(revision 3949)
+++ target-i386/helper.c	(revision 3950)
@@ -2718,6 +2718,7 @@
         break;
     case 8:
         cpu_set_apic_tpr(env, T0);
+        env->cr[8] = T0;
         break;
     default:
         env->cr[reg] = T0;
@@ -4065,6 +4066,7 @@
     int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
     if (int_ctl & V_INTR_MASKING_MASK) {
         env->cr[8] = int_ctl & V_TPR_MASK;
+        cpu_set_apic_tpr(env, env->cr[8]);
         if (env->eflags & IF_MASK)
             env->hflags |= HF_HIF_MASK;
     }
@@ -4376,8 +4378,10 @@
     cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0)) | CR0_PE_MASK);
     cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4)));
     cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3)));
-    if (int_ctl & V_INTR_MASKING_MASK)
+    if (int_ctl & V_INTR_MASKING_MASK) {
         env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr8));
+        cpu_set_apic_tpr(env, env->cr[8]);
+    }
     /* we need to set the efer after the crs so the hidden flags get set properly */
 #ifdef TARGET_X86_64
     env->efer  = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer));

Property changes on: target-i386/helper.c
___________________________________________________________________
Name: cvs2svn:cvs-rev
   - 1.99
   + 1.100

Index: target-i386/cpu.h
===================================================================
--- target-i386/cpu.h	(revision 3949)
+++ target-i386/cpu.h	(revision 3950)
@@ -493,7 +493,7 @@
     SegmentCache gdt; /* only base and limit are used */
     SegmentCache idt; /* only base and limit are used */
 
-    target_ulong cr[5]; /* NOTE: cr1 is unused */
+    target_ulong cr[9]; /* NOTE: cr1, cr5-7 are unused */
     uint32_t a20_mask;
 
     /* FPU state */

Property changes on: target-i386/cpu.h
___________________________________________________________________
Name: cvs2svn:cvs-rev
   - 1.56
   + 1.57