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changeset 243:23150418768a

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[project @ 2003-04-14 22:22:54 by bellard] added 'A' asm constraint
author bellard
date Mon, 14 Apr 2003 22:22:54 +0000
parents 244b2df32b67
children 825ded62893f
files i386-asm.c
diffstat 1 files changed, 30 insertions(+), 5 deletions(-) [+]
line wrap: on
line diff
--- a/i386-asm.c	Mon Apr 14 22:22:34 2003 +0000
+++ b/i386-asm.c	Mon Apr 14 22:22:54 2003 +0000
@@ -710,19 +710,22 @@
             break;
         str++;
         switch(c) {
+        case 'A':
+            pr = 0;
+            break;
         case 'a':
         case 'b':
         case 'c':
         case 'd':
         case 'S':
         case 'D':
-            pr = 0;
-        break;
-        case 'q':
             pr = 1;
             break;
+        case 'q':
+            pr = 2;
+            break;
         case 'r':
-            pr = 2;
+            pr = 3;
             break;
         case 'N':
         case 'M':
@@ -730,7 +733,7 @@
         case 'i':
         case 'm':
         case 'g':
-            pr = 3;
+            pr = 4;
             break;
         default:
             error("unknown constraint '%c'", c);
@@ -817,6 +820,15 @@
     try_next:
         c = *str++;
         switch(c) {
+        case 'A':
+            /* allocate both eax and edx */
+            if (regs_allocated[TREG_EAX] || regs_allocated[TREG_EDX])
+                goto try_next;
+            op->is_llong = 1;
+            op->reg = TREG_EAX;
+            regs_allocated[TREG_EAX] = 1;
+            regs_allocated[TREG_EDX] = 1;
+            break;
         case 'a':
             reg = TREG_EAX;
             goto alloc_reg;
@@ -854,6 +866,7 @@
             goto try_next;
         reg_found:
             /* now we can reload in the register */
+            op->is_llong = 0;
             op->reg = reg;
             regs_allocated[reg] = 1;
             break;
@@ -1027,6 +1040,12 @@
             op = &operands[i];
             if (op->reg >= 0) {
                 load(op->reg, op->vt);
+                if (op->is_llong) {
+                    SValue sv;
+                    sv = *op->vt;
+                    sv.c.ul += 4;
+                    load(TREG_EDX, &sv);
+                }
             }
         }
         /* generate load code for output memory references */
@@ -1045,6 +1064,12 @@
             op = &operands[i];
             if (op->reg >= 0 && ((op->vt->r & VT_VALMASK) != VT_LLOCAL)) {
                 store(op->reg, op->vt);
+                if (op->is_llong) {
+                    SValue sv;
+                    sv = *op->vt;
+                    sv.c.ul += 4;
+                    store(TREG_EDX, &sv);
+                }
             }
         }
         /* generate reg restore code */